Current sample-and-hold-circuit, a/d converter and a method for operating a current sample-and-hold circuit

ABSTRACT

The invention relates to a current sample-and-hold circuit comprising several sub-circuits, in which a current signal is stored. At least one of said sub-circuits contains a switch. The inventive current hold-and-sample circuit is characterized in that each of the sub-circuits contains a linear resistor, which is connected in such a way that the current signal generates a voltage drop across the resistor, that each of the sub-circuits contains at least one inverting control amplifier, which sets an initial current of the circuit in a hold operational mode, thus inducing a voltage drop across the resistor, said voltage drop being substantially as great as the voltage drop across the resistor before the hold operational mode.

The invention relates to a current sample-and-hold circuit having aplurality of subcircuits which store a current signal, at least one ofthe subcircuits containing a switch which is at a constant potential.

The invention also relates to an analog/digital converter having atleast one current sample-and-hold circuit.

The invention also relates to a method for operating a currentsample-and-hold circuit.

The accuracy of analog/digital converters depends, inter alia, on thesample-and-hold circuits used (Sample & Hold Circuits), which provide ananalog input signal at discrete times for subsequent quantization.

Particularly in the case of sample & hold circuits using CMOStechnology, whose information transfer is effected in the voltagedomain, the relevant switching elements are known to need to be at avirtual ground potential at any turn-off time (zero-switching technique)in order to attain a high level of accuracy. The turn-off pulse thusalways injects the same fault charge into the sampling capacitance,which avoids sampling errors dependent on the input signal and resultsin a high level of sampling accuracy.

If currents are used for information transfer instead of voltages(current mode), then the current is usually attributed to a voltagewhich can be stored in a capacitor. Since the switching transistor'schannel is at a potential which is dependent on the input signal in mostarchitectures, the fault charge injected during the turn-off operationdistorts the sampling result. By using an operational amplifier, azero-switching technique can also be implemented in this case, but thishas negative effects on the bandwidth of the circuit.

A generic current sample-and-hold circuit is known from the article byJonsson and S. Eriksson: “New Clock-Feedthrough Compensation Scheme forSwitched-Current Circuits”, Electr. Lett., Vol. 29, No. 16, pp.1446-1447, August 1993. This circuit requires four subcircuits forstoring the signal.

Another generic current sample-and-hold circuit is known from the bookby B. Jonsson et al., Switched-Current Circuits: From Building Blocks toMixed Analog-Digital Systems, Stockholm 1999, pp. 27-33.

The use of switching elements, for example n-MOS transistors, which areat the same virtual ground potential at any time is referred to as azero-switching technique. In contrast to the use of transmission gates,consisting of n-MOS and p-MOS transistors, the hold time can bedetermined very exactly in this case, since a single signal is used toturn off all the switches simultaneously, especially since all theswitching transistors are always at the same constant potential.Particularly in the case of fast analog/digital converters (ADCs), suchas are used, by way of example, to process video signals or otherradio-frequency signals, the jitter, that is to say the discrepancies inthe turn-off time, otherwise significantly determines the accuracy ofthe sampling element. In addition, the turn-off pulse always injects thesame fault charge into the sampling capacitance when the switchpotential is constant, which avoids sampling errors which are dependenton the input signal. The invention comprises a simple method fordiscrete-time current signal sampling, where the relevant switchingelements are always at a virtual ground potential, and this results inthe aforementioned advantages (low jitter, constant charge-injection).Its low complexity means that it is particularly suitable for highsignal bandwidths.

To reduce the signal-dependent sampling errors which cannot beeliminated by virtue of a fully differential design, various measuresare taken which are known by the terms n-step principle, zero-switchingtechnique and replica technique.

In addition, U.S. Pat. No. 5,227,676 describes a current sample-and-holdcircuit having a subcircuit which is used for storing the current. Theknown current sample-and-hold circuit also contains linear resistors,which are actually arranged outside the subcircuit. A similar situationapplies to the current sample-and-hold circuit described in (B. Razavi,A 200-MHz 15-mW BiCMOS Sample-and-Hold Amplifier with 3 V Supply, IEEEJournal of Solid State Circuits, Vol. 30, No. 12, pp. 1326-1332,December 1995).

The invention is based on the object of providing a currentsample-and-hold circuit in which signal-dependent sampling errors areeliminated as far as possible.

The invention achieves this object by virtue of a generic currentsample-and-hold circuit being designed such that the subcircuits eachcontain at least one linear resistor which is connected such that thecurrent signal produces a voltage drop across a resistor, and such thatthe subcircuits each contain at least one control amplifier which isoperated so as to cause inversion and, in a hold mode, sets an outputcurrent for the circuit which causes a voltage drop across the resistorwhich is essentially the same size as the voltage drop across theresistor before the hold mode.

A simple structure to the circuit and a simple clock sequence for thesignals means that only a few turn-off pulses, preferably only a singleturn-off pulse, are required. Consequently, the current sample-and-holdcircuit is also particularly suitable for radio-frequency applications,for example for processing video signals.

Preferably, the invention includes a fully differential design for thecircuit. A differential design allows errors to be suppressed.

The invention also relates to performance of a method for operating acurrent sample-and-hold circuit having a plurality of subcircuits, thesubcircuits each storing a current signal, such that the current signalproduces a voltage drop across a resistor, and such that a controlamplifier which the subcircuits contain and which is operated so as tocause inversion sets, in a hold mode, an output current for the circuitwhich causes a voltage drop across the resistor which is essentially thesame size as the voltage drop across the resistor before the hold mode.

One preferred embodiment of the current sample-and-hold circuit and ofthe method for operating is distinguished in that at least twosubcircuits can be connected to one another using a connecting switch.

In this context, it is particularly expedient that the connecting switchis arranged such that, in a turned-on state of the connecting switch, acharging current for storage capacitors is produced solely by thecurrent signal.

It is also advantageous to design the current sample-and-hold circuitsuch, or to perform the method for operating the current sample-and-holdcircuit such, that all the subcircuits contain switches which are eachat the same potential.

Other advantages, peculiarities and expedient developments of theinvention can be found in the subclaims and in the description below ofpreferred exemplary embodiments with reference to the drawings, inwhich:

FIG. 1 shows a basic circuit diagram of a sample-and-hold circuit forvoltage signals,

FIG. 2 shows a basic circuit diagram of a fully differentialsample-and-hold circuit in accordance with the invention, and

FIG. 3 shows a detailed illustration of a preferred circuit inaccordance with the invention.

FIG. 1 shows a basic illustration of a sample-and-hold circuit forvoltage signals with switches S_(1a) and S_(1b). The switches S_(1a) andS_(1b), which determine the accuracy, are at a constant potential andtherefore inject the same fault charge independently of signal.

A particularly expedient embodiment of the invention is implemented by acurrent sample-and-hold circuit in which the switching elements arealways at the same potential. Such a current sample-and-hold circuit isshown by way of example in FIG. 2. An input current is linearlyconverted into a voltage in a resistor R. One connection of a switchingtransistor S_(SH) is connected to a capacitor C. When this switchingtransistor is off, the storage capacitor C, the amplifier V and thetransistor M form a control loop which keeps the potential on theresistor constant. In this form, the circuit represents a current sourcewith a high output impedance which holds the sampled current.

Before holding, the charging current for the capacitor C needs to besupplied by the shorted inverting amplifier V, which can require highcurrents. With a fully differential design for the sampling element,this displacement current is supplied via the switch S_(inter) in thesecond path, so that the output current demands on the invertingamplifiers are low.

The amplifier V can be produced, by way of example, by a simple cascodecircuit, as a result of which the overall circuit permits very high bandwidths.

An important advantage of the invention is that a currentsample-and-hold element is produced in which the relevant switchingelements are at a fixed potential, without needing to use complicated(=bandwidth-limiting) operational amplifier structures. The fullydifferential design allows the demands on the amplifier circuit V to bekept down.

Before the hold time, the differential input current is discharged toground via the resistors, which results in a voltage across the resistorwhich is proportional to the current. This voltage is on one plate ofthe capacitors C, whose other connection is at a virtual groundpotential stipulated by the inverting control amplifiers (dashed boxes)shorted by S_(SH).

At the hold time, the switches S_(SH) and S_(inter) are turned offsimultaneously and the input switches are then switched over. Theinverting control amplifier now has the task of producing an outputcurrent which results in a voltage drop across the resistor at theoriginal level. To achieve the required output impedance of the currentsource, the control loop, consisting of the storage capacitor C, theinverting amplifier and the control transistor above the resistor, needsto have sufficient gain.

In the fully differential embodiment of the circuit, the switchS_(inter) is used to derive the charging current for the storagecapacitors solely from the signal current. This reduces the demands onthe inverting control amplifiers, which would otherwise need todischarge the charging current for the storage capacitors.

The resistors can also have a nonlinear characteristic curve, forexample when in the form of MOS transistors in the triode domain. As aresult, the capacitance charging currents in the two signal paths nolonger compensate for one another exactly, which means that thedifferential current needs to be supplied by the shorted controlamplifiers.

An advantage of this solution is that the relevant switching elementsalways have the same, constant potential at the turn-off time. Thissignificantly reduces sampling errors resulting from jitter andcharge-injection.

The simple structure and the simple clock sequence (a single turn-offpulse) for the circuit makes it particularly suitable for broadbandapplications, with the implemented zero-switching techniquesimultaneously allowing a high degree of linearity.

List of Reference Symbols

C Capacitor

M Transistor

Q Fault charge amount

R Resistor

S Switch

S_(1a) Switch

S_(1b) Switch

S_(inter) Switch

S_(SH) Switching transistor

V Amplifier

What is claimed is:
 1. A current sample-and-hold circuit having aplurality of subcircuits which store a current signal, at least one ofthe subcircuits containing a switch, characterized in that thesubcircuits each contain at least one linear resistor which is connectedsuch that the current signal produces a voltage drop across the onelinear resistor, and in that the subcircuits each contain at least oneinverting control amplifier which in a hold mode, sets an output currentfor the current sample-and-hold circuit which causes a voltage dropacross the one linear resistor which is essentially the same size as avoltage drop across the one linear resistor before the hold mode.
 2. Thecurrent sample-and-hold circuit as claimed in claim 1, characterized inthat at least two subcircuits can be connected to one another using aconnecting switch (S_(inter)).
 3. The current sample-and-hold circuit asclaimed in claim 2, characterized in that the connecting switch(S_(inter)) is arranged such that, in a turned-on state of theconnecting switch, a charging current for storage capacitors is producedsolely by the current signal.
 4. The current sample-and-hold circuit asclaimed in claim 1, characterized in that all the subcircuits containswitches which are each at the same potential.
 5. A method for operatinga current sample-and-hold circuit having a plurality of subcircuits, thesubcircuits each storing a current signal, characterized in that thecurrent signal produces a voltage drop across a resistor, and in that aninverting control amplifier which the subcircuits contain sets, in ahold mode, an output current for the current sample-and-hold circuitwhich causes a voltage drop across the resistor which is essentially thesame size as a voltage drop across the resistor before the hold mode.